View IS43R16320A_1451325.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. ? 1-800-379-4774 1 rev. a 03/22/06 issi ? IS43R16320A copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? clock frequency: 166 mhz ? power supply (v dd and v ddq ) ddr 333: 2.5v + 0.2v ? sstl 2 interface ? four internal banks to hide row pre-charge and active operations ? commands and addresses register on positive clock edges (ck) ? bi-directional data strobe signal for data cap- ture ? differential clock inputs (ck and ck ) for two data accesses per clock cycle ? data mask feature for writes supported ? dll aligns data i/o and data strobe transitions with clock inputs ? programmable burst length for read and write operations ? programmable cas latency (2 or 2.5 clocks) ? programmable burst sequence: sequential or interleaved ? burst concatenation and truncation supported for maximum data throughput ? auto pre-charge option for each read or write burst ? 8192 refresh cycles every 64ms ? auto refresh and self refresh modes ? pre-charge power down and active power down modes ? lead-free package 32meg x 16 512-mbit ddr sdram march 2006 device overview issi?s 512-mbit ddr sdram achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. the 536,870,912-bit memory array is internally organized as four banks of 128m-bit to allow concurrent operations. the pipeline allows read and write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. the programmable features of burst length, burst sequence and cas latency enable further advantages. the device is available in 16-bit data word size. input data is regis- tered on the i/o pins on both edges of data strobe signal(s), while output data is referenced to both edges of data strobe and both edges of ck. commands are registered on the positive edges of ck. auto refresh, active power down, and pre-charge power down modes are enabled by using clock enable (cke) and other inputs in an industry-standard sequence. all input and output voltage levels are compatible with sstl 2. key timing parameters parameter -6 unit ddr333 clock cycle time cas latency = 3 ? ns cas latency = 2.5 6 ns cas latency = 2 7.5 ns clock frequency cas latency = 3 ? mhz cas latency = 2.5 166 mhz cas latency = 2 133 mhz
2 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A pin configurations 66 pin tsop - type ii for x16 pin descriptions a0-a12 row address input a0-a9 column address input ba0, ba1 bank select address dq0 to dq15 data i/o ck, ck system clock input cke clock enable cs chip select ras row address strobe command cas column address strobe command v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v ddq ldqs nc vdd dnu ldm we cas ras cs nc ba0 ba1 a10 a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ssq udqs nc vref vss udm ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss we write enable ldm, udm x16 input mask ldqs, udqs data strobe v dd power vss ground v ddq power supply for i/o pin vss q ground for i/o pin v ref input reference voltage dnu do not use nc no connection
integrated silicon solution, inc. ? 1-800-379-4774 3 rev. a 03/22/06 issi ? IS43R16320A mode reg i ster operation a8 a7 a6 a5 a4 cas late n c y a3 a2 a1 a0 burst length bt a d dress bus cas latency a6 a5 a4 latency 0 0 0 r eserved 0 0 1 r eserved 01 0 2 0 1 1 1 0 0 r eserved 10 1 reserved reserved 11 0 2 . 5 1 1 1 r eserved burs t len gth a2 a1 a0 burst length 0 0 0 r eser ved 00 1 2 01 0 4 01 1 8 1 0 0 r eser ved 1 0 1 r eser ved 1 1 0 r eser ved 1 1 1 r eser ved ba1 ba0 a1 1 a 10 a9 0* 0 * mode register opera ting mod e * b a 0 a nd ba1 must be 0, 0 to select th e mode register (vs. the e x tende d mode register) . a12 - a9 a8 a 7 a6 - a0 operating mode 00 0 v a l i d norma l oper ation do n ot reset dll 01 0 v a l i d norma l oper ation in d ll reset reserved a3 burst ty p e 0 s e quential 1 interleave a12
4 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A notes: 1. for a burst length of two, a1-a i selects the two-data-e lement block; a0 se lects the first acce ss within the block. 2. for a burst length of four, a2-a i selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-a i selects the eight-data- element block; a0-a2 selects th e first access within the block. 4. whenever a boundary of the block is reached within a give n sequence above, the following access wraps within the block. burst type accesses within a given burst may be programmed to be either sequ ential or interleaved; this is re ferred to as the burst type and is selected via bit a3. the ordering of accesses within a bu rst is determined by the burst length, the burst type and the s tart- ing col umn address, as shown in bur st definition. read latency the read latency, or cas latency, is the delay, in clock cycle s, between the registration of a read command and the availabilit y of the first burst of output data. the latency can be programmed 2 or 2.5 clocks for ddr333. if a read command is registered at clock edge n, and the latency is m clocks, the data is availabl e nominally co incident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. burst definition burst length starting column address order of accesses within a burst a2 a1 a0 type = sequential type = interleaved 2 0 0 - 1 0 - 1 11 - 0 1 - 0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
integrated silicon solution, inc. ? 1-800-379-4774 5 rev. a 03/22/06 issi ? IS43R16320A read command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca a0- a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
6 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A write command ba high ca = column address ba = bank address cke cs ras cas we a10 ba0, ba1 don?t care ca a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck
integrated silicon solution, inc. ? 1-800-379-4774 7 rev. a 03/22/06 issi ? IS43R16320A cap acit ance parameter s ymbol min. max. unit s n otes input capacitan ce: c k , ck ci 1 2.0 3.0 pf 1 delta inpu t capacita nce: c k , ck delta ci 1 0.25 pf 1 input capacitan ce: all o ther input-o nly pins ( except d m ) ci 2 2.0 3.0 pf 1 delta inpu t capacita nce: all other input- only pins (except dm) delta ci 2 0.5 pf 1 input /outpu t capacita nce: d q , d q s, d m c io 4.0 5.0 pf 1, 2 delta inpu t/outp ut capacit ance: dq, dqs, d m delta c io 0.5 pf 1 1. v ddq = v dd = 2.5v 0. 2v (minimum r ange to maximum rang e), f = 100mh z , t a = 25 c, vo dc = v ddq/2 , vo p eak -pe a k = 0 .2v. 2. although dm is an input-only pin, the in put ca p acit ance of t his pin must model th e inp ut cap a cit ance of the dq and dqs pins. th i s is r equir ed to match input pr op agation time s o f dq, dqs a nd dm in the system. dc electrical characteristics and operating conditions ( 0 c < t a < 7 0 o c; v d d q = v dd = + 2 . 5v 0 . 2v (ddr 3 33); see ac char a c t e r i s t ics) sy mbol parameter min max u nit s n o tes v dd supply voltag e ddr 333 2.3 2.7 v 1 v ddq i/o supply v o ltage d dr333 2.3 2.7 v 1 v 1, 2 v ss , v ssq supply voltag e i/o supply v o ltage 00 v v ref i/o refe rence volt age 0.49 x v ddq 0.51 x v ddq v tt i/o t erminatio n voltage (system) v ref - 0.04 v ref + 0.04 v 1, 3 v i h (dc) inp ut high (logic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il(dc) inp ut low ( logic0) v o ltage -0.3 v ref - 0.15 v 1 v i n (dc) inp ut voltag e leve l , ck a nd ck inputs -0.3 v ddq + 0.3 v 1 v i d (dc) inp ut differential voltage , ck and ck inp uts 0.30 v ddq + 0.6 v 1, 4 v i x (dc) inp ut crossing point voltage, ck an d ck inputs 0.30 v ddq + 0.6 v 1, 4 vi ra t io v - i matching pullup c urre nt to pulldow n curr ent ratio 0.71 1.4 2 -2 -5 5 5 i i i n p u t l e a k a g e c u r r e n t any input 0v < v in < v d d ; ( a l l o t h e r p i n s n o t u n d e r t e s t = 0 v ) a 1 i oz output le akage curr ent ( d qs ar e disabled; 0v < v ou t < v ddq a1 1. i nputs are not r ecognized as valid until v ref s t abili zes. 2. v ref is e x pected to b e equal to 0.5 v ddq of the tr ansmitting device, a nd to track va ria ti ons in the dc level of the same. peak-to- peak noise on v ref may not exce ed 2% of the dc value. 3. v tt is not applied dir ectly to the device. v tt is a system supply for signal termination re sisto r s, is expect ed to be set equal to v ref , and must track va ria tions in the dc level of v ref . 4. v id is the magnitude o f the dif fer ence between the in put level on ck and the in put level on ck . 5. t he ratio of the p ullup curre nt to the pulldown curr ent is s pecified for t he same temperatu r e and volt age, over th e entire te mper ature a nd volt age ran ge, for de vice drain to source volt ages for 0.25 volt s to 1.0 volt s. f or a g i ven output, it r epresent s the maximum d if fer ence betw een pullup and pulldow n drive r s due to pr ocess var i a tion. m m
8 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A normal strength driver pulldown and pullup characteristics 1. the full variation in driver pulldown current from minimum to maximum process, temperatur e and voltage will lie within the outer bounding lines of the v-i curve. 2. it is recommended that the ?typical? ibis pulldown v-i curve lie within the shaded region of the v-i curve. 3. the full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve. 4. it is recommended that the ?typical? ibis pullup v- i curve lie within the shaded region of the v-i curve. i oh output current: nominal strength driver high current (v out = v ddq -0.373v, min v ref , min v tt ) low current (v out = 0.373v, max v ref , max v tt ) ? 16.8 ma 1 i ol 16.8 i ohw output current: half- strength driver high current (v out = v ddq -0.763v, min v ref , min v tt ) low current (v out = 0.763v, max v ref , max v tt ) ? 9.0 ma 1 i olw 9.0 normal strength driver pulldown characteristics dc electrical characteristics and operating conditions (0c < t a < 70 o c; v ddq = v dd = + 2.5v 0.2v (ddr333); see ac charact eristics) symbol parameter min max units notes 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variati ons in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck . 5. the ratio of the pullup current to the pulldown current is s pecified for the same temperature and voltage, over the entire te mperature and voltage range, for device drain to source voltages for 0.25 volt s to 1.0 volts. for a given output, it represents the maximum d ifference between pullup and pulldown drivers due to process variation. 0 2.7 0 140 i out (ma) v out (v) maximum typical high typical low minimum
integrated silicon solution, inc. ? 1-800-379-4774 9 rev. a 03/22/06 issi ? IS43R16320A 5. the full variation i n the ratio of the maximum to minimum pullu p and pulldo wn current will not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the ?typical? ibis pullup to ?typical? ibis pulldown current should be unity + 10%, for device drain to source voltages from 0.1 to 1.0. this specification is a design objective only. it is not guaranteed. 7. these characteristics are intended to obey the sstl_2 class ii standard. 8. this specification is intended for ddr sdram only. normal strength driver pullup characteristics maximum typical high typical low minimum v out (v) 2.7 0 0 -200 i out (ma)
10 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A normal strength driver pu lldown and pullup currents pulldown current (ma) pullup current (ma) voltage (v) typical low typical high min max typical low typical high min max 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.9 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 normal strength driver evaluation conditions typical minimum maximum temperature (t ambient ) 25 c 70 c0 c v ddq 2.5v 2.3v 2.7v process conditions typical process slow-slow process fast-fast process
integrated silicon solution, inc. ? 1-800-379-4774 11 rev. a 03/22/06 issi ? IS43R16320A ac characteristics (notes 1-5 apply to the following tables; electrical characteri stics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and electr ical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operat ion are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. re fer to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environm ent, but input timing is still referenced to v ref (or to the crossing point for ck, ck ), and parameter specifications are guar anteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e . the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. ac output load circuit diagrams 50 ? timing reference point output (v out ) 30pf v tt
12 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A ac input operating conditions (0 c < t a < 7 0 o c v dd = v d d q = 2 . 5v + 0 . 2v (ddr3 3 3); s e e ac ch a rac t e ris t ics) symbo l parameter /conditio n min m ax unit notes v ih ( a c ) in put high (log ic 1) voltage, d q , d q s, and dm sign als v ref + 0.31 v 1 , 2 v il(ac) in put low ( logic 0) voltag e, dq, dqs, and dm signals v ref - 0 .31 v 1, 2 v id ( a c ) in put differential volta ge, ck and c k in puts 0.62 v ddq + 0.6 v 1, 2, 3 v ix ( a c ) in put cro s sin g point voltage, c k and ck inputs 0.5*v ddq - 0.2 0 .5*v ddq + 0.2 v 1, 2, 4 1. i nput slew r ate = 1v/ns 2. input s ar e not r ecog nized as va lid until v ref st abili zes. 3. v id is the magnitude o f the dif fer ence between the in put level on ck and the in put level on ck . 4. t he va lue of v ix is e x pected to e qual 0 .5*v ddq of t he transmitting device and must track var i a tions in the dc level of the same. i dd s p ecifications and conditions (0 c < t < a 70 o c v dd = v dd q = 2. 5v + 0. 2v (ddr 33 3); se e ac cha ract e rist ics) symbol paramete r/cond ition ddr333 (6 k) t ck =6ns un it n o tes i dd0 operat ing cu r r en t : one ban k; active / precharge ; t rc = t rc (mi n); dq , dm, and dqs inputs changing twice per cloc k cycle; addr ess an d co ntrol inputs changing once per clock cycle 96 m a 1 i dd1 operat ing current : one ban k; active / read / pr echarge; bur s t = 2; t rc = t rc (mi n ); c l = 2.5 ; i out = 0ma; addr ess and con t rol in puts chan ging once per clock cycle 99 m a 1 i dd2p precha r ge power dow n standby current : all banks idle; powe r down mode; cke < v il (ma x ) m a 1 i dd2n id le stan dby current: cs > v ih ( min); al l banks i d le; cke > v ih (mi n ); addr ess and contr ol inputs c hanging once per clock cycle 25 5 m a 1 i dd3p act ive power do wn stan db y curren t : one ba nk active; pow er do wn mode; cke < v il (max ) 11 m a 1 i dd3n act i ve stan db y cu r r en t : one bank; active / prechar ge; cs > v ih (mi n ); cke > v ih (mi n); t rc = t ras ( m ax); dq, dm, an d dqs inputs changing twice per clock cycle ; address and control inputs chan ging once p er clock cy cle 45 m a 1 i dd4r operat ing current : one bank; b u rst = 2; reads ; continuous burst; addr ess and contr ol inputs changing once per clock cycle; dq and dqs outputs changing twice per clo c k cycle; cl = 2.5; i out = 0ma 104 m a 1 i dd4 w operat ing cu r r en t : one b ank; burst = 2; wr it es; continuous b urst; addr ess and contr ol inputs changing once per clock cycle; dq and dqs in puts changing twice per clo c k cycle; cl = 2.5 117 m a 1 i dd5 au to -ref re sh cu rre nt : t rc = t rfc ( m in) 193 m a 1 i dd6 self -ref r e sh cu rr e n t : c k e < 0.2v 5 m a 1, 2 i dd7 operat ing curren t: f our bank; four bank int erleaving with bl = 4, ad dress and co ntrol input s r andomly chang ing; 50% of dat a changing at every tra ns- fer; t rc = t rc (min ); i out = 0ma. 307 m a 1 1. i dd specif icatio ns ar e tested after the device is p r oper ly in itialized. 2. enables on-chip refr esh a nd addre s s counters. v alues are aver aged from high a nd lo w temp value s using x1 6 devices.
integrated silicon solution, inc. ? 1-800-379-4774 13 rev. a 03/22/06 issi ? IS43R16320A electrical characteristi cs & ac t i ming - absolute s pe cific ations (0 c < t a < 7 0 o c v dd = v d d q = 2 . 5v + 0 . 2v (ddr3 3 3); s e e ac ch a rac t e ris t ics) symbo l p arame ter dd r3 33 (6 k ) unit notes min max t ac dq o u t p ut a cce ss tim e f r om ck /ck -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 n s 1 - 4 t dqs c k dq s out p ut access time from c k / c k -0.6 +0.6 n s 1 - 4 t ch ck hig h-level wid th 0. 45 0. 55 t ck 1-4 t cl ck low- level widt h 0. 45 0. 55 t ck 1-4 t ck clock c ycle time cl = 3.0 n s 1 -4 cl = 2. 5 6 1 2 ns 1-4 cl = 2. 0 7 .5 1 2 ns 1-4 t dh dq an d dm inp ut hol d t i me 0. 45 ns 1-4, 15, 16 t ds dq an d dm inp ut set up time 0. 45 ns 1-4, 15, 16 t ipw i npu t pulse widt h 2 .2 ns 2- 4, 12 t dipw dq an d dm inp u t pul s e wid th (ea c h in put) 1 .75 n s 1 -4 t hz dat a-o ut hig h-imp edance t i me fr om ck /ck ns 1-4, 5 t lz dat a-o ut low- impeda nce time f r om ck/c k ns 1-4, 5 t dq sq dqs - dq sk e w (dq s & asso cia t e d dq sign als) ts op package +0.45 +0.4 ns 1-4 b g a pa ck ag e ns 1-4 t hp minimum half clk period f o r any given cycle; de fin ed by clk high (t ch ) or clk low (t cl ) ti m e min (t cl , t ch ) t ck 1-4 t qh dat a out put hold t i me fro m dq s t hp - t qhs t ck 1-4 t qh s dat a hold s k e w fact or ts op package 0 . 5 5 t ck 1-4 b g a pa ck ag e 0 .5 t ck 1-4 t dq s s wri t e command t o 1st dqs la tchin g transition 0. 75 1. 25 t ck 1-4 t dqs h dqs i nput h i gh pul se widt h (writ e cycle ) 0. 35 t ck 1-4 t dqsl dqs i nput l o w p u lse width ( w r i te cycle) 0.35 t ck 1-4 t dss dqs f all ing edge t o ck se tup t i me (writ e cycle ) 0 .2 t ck 1-4 t dsh dqs f all ing edge h old ti me f r om ck (writ e cycle) 0 .2 t ck 1-4 t mr d mode r egister set command cycle t ime 2 t ck 1-4 t wpres wri t e pr eamble set up t i me 0 n s 1 -4, 7 t wpst wri t e po st ambl e 0 . 4 0 0 . 6 0 t ck 1-4, 6 t wpre wri t e pr eamble 0. 25 t ck 1-4 t ih a ddress and cont rol inp u t ho ld time ( f a s t sle w r a te ) n s 2-4 , 9, 11, 1 2 t is a ddress and cont rol inp u t set up ti m e ( f a s t sle w r a te ) n s 2-4 , 9, 11, 1 2 t ih a ddress and cont rol inp u t ho ld time (slo w slew rat e ) 0 .8 n s 2-4, 10-1 2, 14 t is a ddress and cont rol inp u t set up ti m e (slo w slew rat e ) 0 .8 n s 2-4, 10 , 1 1 , 12, 1 4 t rpr e rea d p r eamb l e 0 .9 1.1 t ck 1-4 t rps t r e ad po st am bl e 0 .4 0 0 .6 0 t ck 1-4 0.75 0.75
14 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A t ras a c t i ve to pr echarg e comma nd 42 12 0,0 00 ns 1-4 t rc ac tive t o a c tive /a u to - r e f r es h co m m a nd p e r iod 6 0 n s 1 - 4 t rfc a uto -ref r esh t o a c t i ve/ a ut o-r ef r esh co mmand per iod 72 ns 1-4 t rcd ac ti ve t o r e a d or w r i t e de l a y 1 8 n s 1 - 4 t rap a c t i ve to read comma nd with a uto precha rge min (t rcd , t ras ) ns 1-4 t rp p recharg e comma nd peri o d 1 8 n s 1 -4 t rrd a c t i ve bank a to act i ve bank b co mmand 12 ns 1-4 t wr wri t e re co ve ry t i me 15 ns us 1-4 t dal a uto pr echarg e wr ite re co ve ry + precha rge t i me (t wr /t ck ) + (t rp /t ck ) t ck 1- 4, 13 t wtr i nt erna l wri t e t o read comman d d elay 1 t ck 1-4 t pdex p o wer down exit t i me 6 n s 1 -4 t xsnr e x it se lf- r ef resh to no n-re ad co mmand 75 ns 1-4 t xsrd e x it se lf- r ef resh to re ad command 2 00 t ck 1-4 1-4, 8 t re f i a v er age pe riodi c ref r esh in ter v a l 7.8 electrical characteristi cs & ac t i ming - absolute s pe cific ations (0 c < t a < 7 0 o c v dd = v d d q = 2 . 5v + 0 . 2v (ddr3 3 3); s e e ac ch a rac t e ris t ics) symbo l p arame ter dd r3 33 (6 k ) unit notes min max
integrated silicon solution, inc. ? 1-800-379-4774 15 rev. a 03/22/06 issi ? IS43R16320A electrical characteristics & ac timing - absolute specifications notes 1. input slew rate = 1v/ns. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross; the input reference level for signals other than ck/ck is v ref . 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at th e timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific vo ltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic an d meeting the input slew rate specifications of the device. when no writes were previous ly in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in prog ress, dqs could be high, low, or transi tioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefr esh commands can be posted to any given ddr sdram device. 9. for command/address input slew rate 1.0v/ns. slew rate is measured between v oh (ac) and v ol (ac). 10. for command/address input slew rate 0.5v/ns and < 1.0v/ns. slew rate is measured between v oh (ac) and v ol (ac). 11. ck/ck slew rates are 1.0v/ns. 12. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. for each of the terms in parentheses, if not alre ady an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. fo r example, for ddr333 at cl = 2.5, t dal = (15ns/6ns) + (18ns/6ns) = 3 + 3 = 6.
16 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 03/22/06 issi ? IS43R16320A 14. an input setup and hold time derating table is used to increase t is and t ih in the case where the input slew rate is below 0.5 v/ns. 15. an input setup and hold time derating table is used to increase t ds and t dh in the case where the i/o slew rate is below 0.5 v/ns. 16. an i/o delta rise, fall derating table is used to increase t ds and t dh in the case where dq, dm, and dqs slew rates differ. input slew rate delta (t is ) delta (t ih ) unit notes 0.5 v/ns 00p s 1 , 2 0.4 v/ns +50 0 ps 1,2 0.3 v/ns +100 0 ps 1,2 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or te ster characterization and are not necessarily tested on each devi ce. input slew rate delta (t ds ) delta (t dh ) unit notes 0.5 v/ns 00p s 1 , 2 0.4 v/ns +75 +75 ps 1,2 0.3 v/ns +150 +150 ps 1,2 1. i/o slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or te ster characterization and are not necessarily tested on each devi ce. input slew rate delta (t ds ) delta (t dh ) unit notes 0.0 v/ns 0 0 ps 1,2,3,4 0.25 v/ns +50 +50 ps 1,2,3,4 0.5 v/ns +100 +100 ps 1,2,3,4 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. input slew rate is based on the larger of ac to ac delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] for example: slew rate 1 = 0.5 v/ns; slew rate 2 = 0.4 v/ns delta rise, fall = (1/0.5) - (1/0.4) [ns/v] = -0.5 ns/v using the table above, this would result in an increase in t ds and t dh of 100 ps. 4. these derating parameters may be guaranteed by design or te ster characterization and are not necessarily tested on each devi ce.
integrated silicon solution, inc. ? 1-800-379-4774 17 rev. a 03/22/06 issi ? IS43R16320A ordering information commercial range: 0c to +70c frequency speed (ns) order part no. package 166 mhz 6 IS43R16320A-6tl 66-pin tsop-ii, lead-free
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 1 rev. a 08/09/05 plastic tsop 66-pin package code: t (type ii) plastic tsop (t - type ii) millimeters inches symbol min max min max ref. std. no. leads (n) 66 a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 ? ? ? ? b 0.24 0.40 0.009 0.016 c 0.12 0.21 0.005 0.0083 d 22.02 22.42 0.867 0.8827 e1 10.03 10.29 0.395 0.405 e 11.56 11.96 0.455 0.471 e 0.65 bsc 0.026 bsc l 0.40 0.60 0.016 0.024 l1 ? ? ? ? zd 0.71 ref 0.028 ref 0 8 0 8 d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.

▲Up To Search▲

Price & Availability of IS43R16320A

	To Download IS43R16320A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .